Low Power Built-In Self-Test Schemes for Array and Booth Multipliers
نویسندگان
چکیده
منابع مشابه
Effective Built-In Self-Test for Booth Multipliers
0740-7475/98/$10.00 © 1998 IEEE 105 MODULE GENERATORS PROVIDED by library vendors supply chip designers with optimized Booth multipliers, which are widely used as embedded cores in both generalpurpose data path structures and specialized digital signal processors. Designers frequently use Booth multipliers in areaand speedcritical parts of complex ICs. Compared to standard array multipliers, Bo...
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Aiming low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for Modified Booth Multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable Test Pattern Generator (TPG) built of a 4-bit binary and a 4-bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reduc...
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Power consumption has become the most important issue in the design of integrated circuits. The power consumption during manufacturing or in-system test of a circuit can significantly exceed the power consumption during functional operation. The excessive power can lead to false test fails or can result in the permanent degradation or destruction of the device under test. Both effects can signi...
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2001
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2001/67893